View S5933_1073116.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

6290 sequence drive, san diego, california 92121-4358 800-755-2622 fax: 619-450-9885 http://www.amcc.com S5933 32-bit pci ?matchmaker? february 12, 1997 revised october 1998 f e a t u r e s ? pci 2.1 compliant master/slave device ? full 132 mbytes/sec transfer rate ? pci bus operation dc to 33 mhz ? 8/16/32 bit add-on user bus ? four definable pass-thru regions ? two 32 byte fifos ? sync/async add-on bus operation ? mail box registers w/byte level status ? direct mail box data strobe/interrupts ? big/little endian conversions ? direct pci & add-on interrupt pins ? boot loading from nvram or byte wide ? optional expansion bios/post code ? 160 pin pqfp a p p l i c a t i o n s ? high speed networking ? digital video applications ? i/o communications ports ? high speed data input/output ? multimedia communications ? memory interfaces ? high speed data acquisition ? data encryption/decryption ? intel i960 interface ? general purpose pci interfacing d e s c r i p t i o n the pci local bus concept was developed to break the pc data i/o bottleneck and clearly opens the door to increasing system speed and expansion capabilities. the pci local bus moves high speed peripherals from the i/o bus and places them closer to the system?s processor bus, providing faster data transfer between the processor and peripherals. the pci local bus also addresses the industry?s need for a standard that is not directly dependent on the speed, size and type of processor bus. it represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications, such as full-motion video. applied micro circuits corporation (amcc), the premier supplier of single chip solutions, has developed and pro- duced the S5933 to solve the problem of interfacing applications to the pci local bus. the S5933, or ?matchmaker?, is a powerful and flexible pci controller supporting several levels of interface sophistication. at the lowest level, it can serve simply as a pci bus target with modest transfer requirements. for high-performance applications, the S5933 can become a bus master to attain the pci local bus peak transfer capability of 132 mbytes/sec. the matchmaker is an off-the-shelf, low-cost, standard product, which is pci 2.1 compliant. and, since amcc is a member of the pci special interest group, the S5933 has been tested in "compliance workshops" along with other man- ufacturer's pci systems, chip sets and bioss. this removes the burden of compliance testing from the designer and thus significantly reduces development time. utilizing the S5933 allows the designer to focus on the actual application, not debugging the pci interface. the matchmaker allows special direct data accessing between the pci bus and the user application through implemen- tation of four definable pass-thru data channels. each data channel is implemented by defining a host memory segment size and 8/16/32-bit user bus width. the addition of two 32 byte fifos, also used in S5933 bus mastering applications, provides further versatility to data transfer capabilities. fifo dma transfers are supported using address and transfer count registers. four 32-bit mailbox registers coupled with a status register and extensive interrupt capabilities pro- vide flexible user command or message transfers between the two buses. in addition, the S5933 also allows use of an external serial, or byte-wide non-volatile memory to perform any pre-boot initialization requirements and to provide custom expansion bios or post code capability.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 2 S5933 32-bit pci ?matchmaker? p c i l o c a l b u s user application satellite receiver/ modem proprietary backplane graphics/ mpeg/ grabber isdn fddi atm i/o audio serial/parallel nvram configuration space expansion bios amcc add-on local bus interface logic mux/demux buffers S5933 status registers configuration registers mailboxes fifos bus master transfer count & address registers pass-thru data & address registers 2.1 pci local bus interface logic mux/demux buffers read/write control S5933 architecture the block diagram in figure 1 above shows the major functional elements within the S5933. the S5933 provides three physical bus interfaces: the pci local bus, the user local bus referred to as the add-on local bus and the optional serial and byte- wide non-volatile memory buses. data movement between buses can take place through mailbox reg- isters or the fifo data channel, or a user can define and enable one or more of the four pass-thru data channels. S5933 bus master or dma data transfers to and from the pci local bus are performed through the fifo data channel under either host or add-on software control or add-on hardware con- trol using dedicated S5933 signal pins. the S5933 signal pins are shown in figure 2 right. the pci local bus signals are detailed on the left side; add-on local bus signal are detailed on the right side. all additional S5933 device control sig- nals are shown on the lower right side. the S5933 supports a two wire serial nvram bus and a byte-wide eprom/flash bus. this allows the designer to customize the S5933 configuration by loading setup information on system power-up. S5933 register architecture control and configuration of the add-on local bus, and the matchmaker itself, is performed through three primary groups of registers. these groups consist of pci configuration registers, pci operation registers and add-on oper- ation registers. all these registers are user configurable through their associated bus or from an external non-volatile memory device. this section will provide a brief overview of each of these register groups and the optional non-vola- tile interface. add-on bus control S5933 register access pass-thru control/access serial bus config/bios opt. pci local bus S5933 control add-on data bus direct fifo access byte wide config/bios opt. bpclk rdfifo# sysrst# irq# wrfifo# dq[31:0] select# adr[6:2] be[3:0]# rd# wr# ptatn# ptburst# ptnum[1:0]# ptbe[3:0]# ptadr# ptwr ptrdy# rdempty wrfull ea[15:0] eq[7:0] ewr#/sda erd#/scl pclk inta# rst# ad[31:0] c/be[3:0]# frame# devsel# irdy# trdy# idsel# stop# lock# par perr# serr# flt# S5933 gnt# req# mode snv figure 2 figure 1
6290 sequence drive, san diego, california 92121-4358 800-755-2622 3 S5933 32-bit pci ?matchmaker? device id pci status class code base address register 0 base address register 2 base address register 4 reserved space expansion rom base address reserved space built-in self test header type reserved space max. latency min. grant vendor id pci command revision id base address register 1 base address register 3 base address register 5 cacheline size latency timer interrupt line interrupt pin byte 3 byte 2 byte 0 byte 1 address 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch reserved space pci configuration registers all pci compliant devices are required to pro- vide a group of configuration registers for the host system. these registers are polled during power up initialization and contain specific device and add-in card product information including vendor id, device id, revision and the amount of memory required for product operation. the S5933 can either load these reg- isters with default values or initialize them from an external non-volatile memory area called 'configuration space'. the S5933 can accom- modate a total of 256 bytes of external memory for this purpose. the first 64 bytes is reserved for user defined configuration data which is loaded into the pci configuration registers during power-up initialization. the remaining 192 bytes may be used to implement an expan- sion bios or contain add-in card post code. table 1 shows all the S5933 pci configuration registers. pci operation registers the second group of registers are the pci oper- ation registers shown in table 2. this group consists of sixteen 32-bit (dword) registers accessible to the host processor from the pci local bus. these are the main registers through which the pci host configures S5933 operation and communicates with the add-on local bus. these registers encompass the pci bus incoming and outgoing mailboxes, fifo data channel, bus master address and count registers, pass-thru data channel registers and S5933 device status and control registers. add-on bus operation registers the third and last register group consists of the add-on operation registers, shown in table 3. this group of eigh- teen 32-bit (dword) registers is accessible to the add-on local bus. these are the main registers through which the add-on logic configures S5933 operation and communicates with the pci local bus. these registers encompass the add- on bus mailboxes, add-on fifo, dma address/count reg- isters (when add-on initiated bus mastering), pass-thru registers and status/control registers. non-volatile memory interface the S5933 contains a set of pci configuration registers. these registers can be initialized with default values or with designer specified values contained in an external nvram. the nvram can be either a serial (2 kbytes, maximum) or a byte-wide device (64 kbytes, maximum). pci operation registers outgoing mailbox register 1 (omb1) incoming mailbox register 1 (imb1) mailbox empty/full status register (mbef) interrupt control/status register (intcsr) bus master control/status register (mcsr) address offset 00h 10h 34h 38h 3ch outgoing mailbox register 2 (omb2) 04h outgoing mailbox register 3 (omb3) 08h outgoing mailbox register 4 (omb4) 0ch incoming mailbox register 2 (imb2) 14h incoming mailbox register 3 (imb3) 18h incoming mailbox register 4 (imb4) 1ch fifo register port (bidirectional) (fifo) 20h master write address register (mwar) 24h master write transfer count register (mwtc) 28h master read address register (mrar) 2ch master read transfer count register (mrtc) 30h table 2 table 1
6290 sequence drive, san diego, california 92121-4358 800-755-2622 4 S5933 32-bit pci ?matchmaker? add-on bus operation registers incoming mailbox register 1 (aimb1) outgoing mailbox register 1 (aomb1) pass-thru address register (apta) pass-thru data register (aptd) maibox empty/full status register (ambef) interrupt control/status register (aint) general control/status register (arcr) bus master write transfer count (mwtc) address 00h 10h 28h 2ch 34h 38h 3ch 58h incoming mailbox register 2 (aimb2) 04h incoming mailbox register 3 (aimb3) 08h incoming mailbox register 4 (aimb4) 0ch outgoing mailbox register 2 (aomb2) 14h outgoing mailbox register 3 (aomb3) 18h outgoing mailbox register 4 (aomb4) 1ch fifo port (afifo) 20h bus master write address register (mwar) 24h bus master read address register (mrar) 30h bus master read transfer count (mrtc) 5ch the optional nvram allows the add-on card manufac- turer to initialize the S5933 with his specific vendor id and device id numbers along with desired S5933 opera- tion characteristics. the non-volatile memory feature also provides for the expansion bios and post code (power-on-self-test) options on the pci bus. mailbox operation the mailbox registers are divided into two four dword sets. each set is dedicated to one bus for trans- ferring data to the other bus. figure 3 below shows a block diagram of the mailbox section of the S5933. the provision of mailbox registers provides an easy path for the transfer of user information (command, status or parametric data) between the two buses. an empty/full indication for each mailbox register, at the byte level, is determined by polling a status register accessible to both the pci and add-on buses. providing mailbox byte level empty/full indications allows for greater flexibility in 8-, 16- or 32-bit system interfaces. i.e., transferring a single byte to an 8-bit add-on bus without requiring the assembling or disassembling of 32-bit data. the generation of interrupts from mailbox registers is equivalent with the commonly known 'doorbell' interrupt technique. bit locations configured within the S5933?s oper- ation registers select a mailbox and mailbox byte which is to generate an interrupt when full or touched. a mailbox interrupt control register is then used to enable interrupt genera- tion and to select if the interrupt is to be generated on the pci or add-on local bus. pci local bus interrupts may also be generated from direct hardware interfacing due to a unique amcc feature. a dedicated mail- box byte of the S5933 is directly accessible via a set of hardware device signal pins. a single mailbox load signal pin latches add-on bus data directly into the mailbox initiat- ing a pci bus interrupt if enabled. the mailbox data may also be read in a similar manner. this option is shared with the byte wide non-vola- tile memory signal pins. the S5933 must use the serial nvram option for the direct mailbox option signals to be available or they will be assigned to the byte wide at power up. table 3 p c i l o c a l b u s mailbox status register S5933 a d d - o n l o c a l b u s pci mb1 byte 0 pci mb2 byte 0 pci mb3 byte 0 pci mb4 byte 0 pci mb1 byte 1 pci mb2 byte 1 pci mb3 byte 1 pci mb4 byte 1 pci mb1 byte 2 pci mb2 byte 2 pci mb3 byte 2 pci mb4 byte 2 pci mb1 byte 3 pci mb2 byte 3 pci mb3 byte 3 pci mb4 byte 3 add mb1 byte 0 add mb2 byte 0 add mb3 byte 0 add mb4 byte 0 add mb1 byte 1 add mb2 byte 1 add mb3 byte 1 add mb4 byte 1 add mb1 byte 2 add mb2 byte 2 add mb3 byte 2 add mb4 byte 2 add mb1 byte 3 add mb2 byte 3 add mb3 byte 3 add mb4 byte 3 figure 3
6290 sequence drive, san diego, california 92121-4358 800-755-2622 5 S5933 32-bit pci ?matchmaker? pass-thru operation pass-thru operation executes pci bus cycles in real time with the add-on bus. this allows the pci bus to directly read or write to add-on resources. the S5933 allows the designer to declare up to four indi- vidual pass-thru regions. each region may be defined as 8-, 16-, or 32-bits wide, mapped into host memory or i/o space and may be up to 512mb bytes in size. figure 4 right shows a block diagram of the S5933 pass-thru architecture. pass-thru operations are performed in pci target only mode, making this data channel useful for con- verting existing isa or eisa designs over to the fast pci architecture. the pass-thru data channel uti- lizes separate add-on bus signal pins to reflect a pci bus read or write request. add-on logic decodes these signals to determine if it must read or write data to the S5933 to satisfy the request. information decoded includes pci request occurring, the byte lanes involved, the spe- cific pass-thru region accessed and if the request is a burst or single-cycle access. all requested pass-thru address and data information is passed via add-on operation registers. pass-thru operation supports single pci data cycles and pci data bursts. during pci burst operations, the S5933 is capable of transferring data at the full pci bandwidth. should slower add-on logic be implemented, the S5933 auto- matically issues pci bus waits or a host retry indication until the requested transfer is satisfied. fifo pci bus mastering operation fifo pci bus master data transfers are processed by one of two 8-dword fifos. the fifo block diagram is shown in figure 5. the particular fifo selected for a data transfer is dependent only on the direction of data flow and is completely transparent to the user. internal S5933 decode logic selects the fifo that is dedicated to transferring data to the other bus. the way data is transferred by a fifo, is determined by operation and configuration registers contained within the S5933. a fifo may be configured for either pci or add-on initiated bus mastering with programmable byte advance conditions, read vs. write priorities and add-on bus widths. advance conditions allow the fifo to imple- ment 8-, 16- or 32-bit bus widths. configuring the S5933 for bus master operation enables separate address and data count registers, which are loaded with the pci memory address location and number of bytes to be read or written. this is accomplished by either the host cpu or add-on logic. data can be transferred between the two buses trans- parent to the pci host processor, however, the add-on logic is required to service the S5933 add-on local bus. an indication of transfer completion can be seen by polling a status register done bit or S5933 signal pin or enabling a 'transfer count = 0' interrupt to either bus. further fifo configuration bits select 16, 32, or 64 bit endian conversion options for incoming and outgoing data. endian conversion allows an add-on processor and the host to transfer data in their native endian format. other con- figuration bits determine if the add-on local bus width is 8, 16 or 32 bits. 16-bit bus configurations internally steer fifo data from the upper 16 bits of the dword and then to the lower 16-bits on alternate accesses. fifo pointers are then updated when appropriate bytes are accessed. other methods are available for 8-bit or 16-bit add-ons. efficient fifo management configuration schemes unique to the amcc S5933 specify how full or empty a fifo must be before it requests the pci local bus. these criteria include bus requests when any of the 8 dwords are empty, or when four or more dwords are empty. this allows the designer to control how often the S5933 requests the bus. the S5933 always attempts to perform burst operations to empty or fill the fifos. further fifo capabilities over the standard register access methods allow for direct hardware fifo access. this is provided through separate access pins on the S5933. other status output pins allow for easily cascading external fifos to the add-on design. p c i l o c a l b u s S5933 add-on pass-thru read data add-on pass-thru write data a d d - o n l o c a l b u s address latch add-on pass- thru address register figure 4
6290 sequence drive, san diego, california 92121-4358 800-755-2622 6 S5933 32-bit pci ?matchmaker? summary because the pci bus applies to numerous system architectures, it allows a single add-in card hardware design to be created for multiple platforms. the pci standard also provides the bandwidth required for many new, high-perfor- mance applications. the amcc S5933 provides a flexible, low-cost, compliant interface to the pci bus. the architecture of the S5933 makes it an excellent choice for cards being converted from the isa/eisa standard, as well as newer applications requiring high data rates and bus mastering capabilities. these applications include frame grabbers, work station graphics, satellite receivers, modems, isdn/fddi/atm communications and i/o interfaces. the S5933 allows the hardware developer to focus on the actual application development rather than debugging the pci bus interface logic. this significantly shortens design cycles and decreases development costs. p c i l o c a l b u s 32-bit master write address register S5933 a d d - o n l o c a l b u s b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter 32-bit master read address register 30-bit master read count register b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter b0 28-bit master write count register figure 5
6290 sequence drive, san diego, california 92121-4358 800-755-2622 7 S5933 32-bit pci ?matchmaker? S5933 p i n d e s c r i p t i o n s ad[31:0] t /s address/data. address and data are multiplexed on the same pci bus pins. a pci bus transaction consists of an address phase followed by one or more data phases. an address phase occurs on the pclk cycle in which frame# is asserted. a data phase occurs on the pclk cycles in which irdy# and trdy# are both asserted. c/be[3:0]# t/s bus command/byte enable . bus commands and byte enables are multiplexed on the same pins. these pins define the current bus command during an address phase. during a data phase, these pins are used as byte enables, with c/be[0]# enabling byte 0 (lsb) and c/ be[3]# enabling byte 3 (msb). c/be# [3 2 1 0] description 0 0 0 0 interrupt acknowledge 0 0 0 1 special cycle 0 0 1 0 i/o read 0 0 1 1 i/o write 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 memory read 0 1 1 1 memory write 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 configuration read 1 0 1 1 configuration write 1 1 0 0 memory read multiple 1 1 0 1 dual address cycle 1 1 1 0 memory read line 1 1 1 1 memory write and invalidate par t/s parity . parity is always driven as even from all ad[31:0] and c/be[3:0]# signals. the par- ity is valid during the clock following the address phase and is driven by the bus master. during a data phase for write transactions, the bus master sources this signal on the clock following irdy# active; during a data phase for read transactions, this signal is driven by the target and is valid on the clock following trdy# active. the par signal has the same timing as ad[31:0], delayed by one clock. pclk in clock . the rising edge of this signal is the reference upon which all other signals are based except for rst# and inta#. the maximum pclk frequency for the S5933 is 33 mhz and the minimum is dc (0 hz). rst# in reset is used to bring all other signals within the S5933 to a known, consistent state. all pci bus interface output signals are not driven (tri-stated), and open drain signals such as serr# are floated. frame# s/t/s frame . this signal is driven by the current bus master to indicate the beginning and dura- tion of a bus transaction. when frame# is first asserted, it indicates a bus transaction is beginning with a valid addresses and bus command present on ad[31:0] and c/be[3:0]. frame# remains asserted during a burst data transfer and is deasserted to signify the final data phase. irdy# s/t/s initiator ready . this signal is always driven by the bus master to indicate its ability to complete the current data phase. during write transactions, it indicates ad[31:0] contains valid data. wait states occur until both trdy# and irdy# are asserted together.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 8 S5933 32-bit pci ?matchmaker? trdy# s/t/s target ready . this signal is sourced by the selected target and indicates the target is able to complete the current data phase of a bus transaction. for read operation, it indicates that the target is providing valid data on the ad[31:0] pins. wait states occur until both trdy# and irdy# are asserted together. stop# s/t/s stop . the stop signal is driven by a selected target and conveys a request to the bus master to stop the current transaction. lock# in lock . the lock signal provides for the exclusive use of a resource. the S5933 may be locked by one master at a time. the S5933 cannot lock a target when it is a master. idsel in initialization device select . this pin is used as a chip select during configuration read or write transactions. devsel# s/t/s device select . this signal is driven by a target decoding and recognizing its bus address. this signal informs a bus master whether an agent has decoded a current bus cycle. inta# o/d interrupt a . this signal is defined as optional and a level sensitive host interrupt. the inta# is used for any single function device requiring an interrupt capability. req# out request. this signal is sourced by an agent wishing to become the bus master. it is a point- to-point signal and each master has its own req#. gnt# in grant. the gnt# signal is a dedicated, point-to-point signal provided to each potential bus master and signifies that access to the bus has been granted. perr# s/t/s parity error . is used for reporting data parity errors for all bus transactions except for spe- cial cycles. it is driven by the agent receiving data two clock cycles after the parity was detected as an error. this signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition. serr# o/d system error . used to report address and data parity errors on special cycle commands and any other error condition having a catastrophic system impact. scl t/s serial clock . this clock provides timing for transactions on the two-wire serial bus. this signal is intended to be directly connected to one serial non-volatile ram. this pin is shared with the byte-wide interface signal, erd#. sda t/s serial data/address . this bidirectional pin is used to transfer addresses and data to or from a serial nvram. it is an open drain output requiring a 10k external pull-up resistor. this pin is shared with the byte-wide interface signal, ewr#. ea[15:0] t/s external nv memory address. these signals connect directly to the external byte wide or eprom address pins ea0 through ea15. the pci interface controller assembles 32-bit wide accesses through multiple read cycles of the 8-bit device. the address space from 0040h through 007fh is used to preload and initialize the pci configuration registers. should an external nv memory be used, the minimum size required is 128 bytes and the maximum is 64k bytes. when a serial memory is connected to the S5933, the pins ea[7:0] are reconfigured to become hardware add-on to pci mailbox register controls with the ea8 pin as the mailbox load clock. also, the ea15 signal pin will provide an indication that the pci to add-on fifo is full (frf), and the ea14 signal pin will indi- cate whether the add-on to pci fifo is empty (fwe). erd# out external nv memory read control. this pin is asserted during read operations involving the external non-volatile memory. data is transferred into the S5933 during the low to high transition of erd#. this pin is shared with the serial external memory interface signal, scl.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 9 S5933 32-bit pci ?matchmaker? ewr# t/s external nv memory write control. this pin is asserted during write operations involving the external non-volatile memory. data is presented on pins eq[7:0] along with its address on pins ea[15:0] throughout the entire assertion of ewr#. this pin is shared with the serial external memory interface signal, sda. eq[7:0] t/s external memory data bus. these pins are used to directly connect with the data pins of an external non-volatile memory. when a serial memory is connected to the S5933, the pins eq4, eq5, eq6, and eq7 become reconfigured to provide signal pins for bus master- ing control from the add-on interface. dq[31:0] t/s address/data bus . the 32 bit add-on data bus. the dqmode signal configures the bus width for either 32 or 16 bits. all dq[31:0] signals have an internal pull-up. adr[6:2} in address [6:2]. these inputs select which S5933 register is to be read from or written to. to be used in conjunction with select#, be[3:0]# and wr# or rd#. the following table shows the register addresses. adr [6 5 4 3 2] description 0 0 0 1 1 add-on incoming mailbox register 0 0 1 1 1 add-on outgoing mailbox register 0 1 0 1 0 add-on pass-thru address register 0 1 0 1 1 add-on pass-thru data register 0 1 1 0 1 add-on mailbox status register 0 1 1 1 0 add-on interrupt control register 0 1 1 1 1 add-on reset control register 1 0 0 0 0 pass-thru/fifo configuration register be[2:0]# in byte enable [2:0] . provides individual read/write byte enabling during register read or write transactions. be2# enables activity over dq[23:16], be1# enables dq[15:8], and be0# enables dq[7:0]. during read transactions, enables the output driver for each byte lane; for write transactions, serves as an input enable to perform the write to each byte lane. be3#/adr1 in byte enable 3/address 1 . be3#, enables dq[31:24] input drivers for writing data to regis- ters identified by adr[6:2] and enables dq[31:24] output drivers to read registers identi- fied by adr[6:2]. to be used in conjunction with select# and rd# or wr#. adr1, selects the upper or lower word of a dword when a 16 bit wide bus is selected. 1 = lower, 0 = upper. select# in select . enables internal S5933 logic to decode wr#, rd# and adr[6:2] when reading or writing to any add-on register. wr# in write enable . asserting this signal writes dq bus data byte(s) selected by be[3:0]# into the S5933 register defined by select# and adr[6:2]. rd# in read enable . asserting this signal drives data byte(s) selected by be[3:0]# from the S5933 register defined by select# and adr[6:2] onto the dq bus. mode in dq mode . defines the dq bus width when accessing data using wr#, rd#, select# and adr[6:2]#. low = 32-bit wide dq bus. high = 16-bit wide dq bus. when high, the signal be3# is re-assigned to the adr1 signal and only dq[15:0] is active. ptatn# out pass-thru attention . signals a decoded pci to pass-thru region bus cycle. ptatn# is generated to signal add-on logic pass-thru data must be read from or written to the S5933.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 10 S5933 32-bit pci ?matchmaker? ptburst# out pass-thru burst . informs the add-on bus the current pass-thru region decoded pci bus cycle is a burst access. ptrdy# in pass-thru ready . this input indicates when add-on logic has completed a pass-thru cycle and another may be initiated. ptnum[1:0] out pass-thru number . identifies which of the four pass-thru regions the host read/write is requesting. only valid for the duration of ptatn#. 00 = base address register 1, 01 = base address register 2, 10 = base address register 3, 11 = base address register 4. ptbe[3:0]# out pass-thru byte enables . during a pci to pass-thru read, indicates which bytes of a dword is to be written into. during a pci to pass-thru write, indicates which bytes of a dword are valid to read. ptbe[3:0]# are only valid while ptatn# is asserted. ptadr# in pass-thru address . when asserted, the 32-bit pass-thru address register contents is driven onto the dq[31:0] bus. all other add-on control signals must be inactive during the assertion of ptadr#. ptwr out pass-thru write . this signal indicates the current pci to pass-thru bus transaction is a read or write cycle. valid only when ptatn# is active. sysrst# out system reset . an active-low buffered pci bus rst# output signal. the signal is asynchro- nous and can be asserted through software from the pci host interface. bpclk out buffered pci clock . this output is a buffered form of the pci bus clock and has all of the behavioral characteristics of the pci clock (i.e., dc-to-33 mhz capability). irq# out interrupt request . this output signals add-on logic a significant event has occurred as a result of activity within the S5933. flt# in float . floats all S5933 output signals when asserted. this signal is connected to an inter- nal pull-up resistor. snv in serial non-volatile device. this input, when high, indicates that a serial boot device or that no boot device in present. when this pin is low, a byte-wide boot device is present. wrfifo# in write fifo. this signal provides a method to directly write the fifo without having to generate the select# signal or the adr[6:2] value of [01000b] to access the fifo. access width is either 32 bits or 16 bits depending on the data bus size available. this sig- nal is intended for implementing pci dma transfers with the add-on system. this pin has an internal pull-up resistor. rdfifo# in read fifo. this signal provides a method to directly read the fifo without having to generate the select# signal or the adr[6:2] value of [01000b] to access the fifo. access width is either 32 bits or 16 bits depending on the data bus size defined by the mode pin. this signal is intended for implementing pci dma transfers with the add-on system. this pin has an internal pull-up resistor. wrfull out write fifo full. this pin indicates whether the add-on-to-pci bus fifo is able to accept more data. this pin is intended to be used to implement dma hardware on the add-on system bus. a logic low output from this pin can be used to represent a dma write (add-on-to-pci fifo) request. rdemtpy out read fifo empty. this pin indicates whether the read fifo (pci-to-add-on fifo) con- tains data. this pin is intended to be used by the add-on system to control dma transfers from the pci bus to the add-on system bus. a logic low from this pin can be used to rep- resent a dma (pci-to-add-on fifo) request.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 11 S5933 32-bit pci ?matchmaker? synchronous wrfifo# timing notes: rdfifo# dq[31:0] rdempty frf old valid new valid bpclk 1 2 3 4 2. the data 4 signal is cut short due to the de-assertion of rdfifo#. 1. the data 1 valid time is dependent on where rdfifo# is asserted in it's window. 3. the rdempty is an example relative to data 2, if the fifo went empty on data 2. notes: wrfifo# dq[31:0] wrfull fwe old valid new valid bpclk 1 1. the wrfull is an example relative to data 2, if data 2 were to fill the fifo. 2 3 t i m i n g d i a g r a m s synchronous rdfifo# timing
6290 sequence drive, san diego, california 92121-4358 800-755-2622 12 S5933 32-bit pci ?matchmaker? bpclk select# adr[6:2] be[3:0] dq[31:0] rd# 1 rdempty frf 3 2 4 5 6 7 8 multiple synchronous wr# operation bpclk select# adr[6:2] be[3:0]# dq[31:0] wr# 1 2 3 4 5 6 7 8 wrfull fwe multiple synchronous rd# operation
6290 sequence drive, san diego, california 92121-4358 800-755-2622 13 S5933 32-bit pci ?matchmaker? symbol parameter min test conditions notes max units v dd supply voltage high level input voltage low level input voltage high level output voltage low level output voltage 4.75 2.0 -0.5 2.4 - 1 5.25 - 0.8 - 0.55 volts volts volts volts volts to pci spec 2.2 i out = -2 ma v ih v il v oh v ol i out = 3 ma, 6 ma high input leakage current low input leakage current - 2 2 70 -70 m a m a i ih i il v in = 2.7 vdc v in = 0.5 vdc - input pin capacitance clk pin capacitance idsel pin capacitance - 5 - 3 10 12 8 pf pf pf c in c clk c idsel a b s o l u t e m a x i m u m r a t i n g s supply voltage range (v dd core) -0.3 v to 7.0 v input pin voltage range -0.5 v to vdd + 0.5 v storage temperature range -55 to 125 c ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to this device. these are stress ratings only. r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s notes: 1. pci bus signals without pull-up resistors will provide the 3 ma output current. signals which require a pull-up resistor (frame#, trdy#, irdy#, devsel#, stop#, serr# and perr#) will provide 6 ma output current. 2. input leakage applies to all inputs and bidirectional buffers. 3. the pci specification limits all pci inputs not located on the motherboard to 10 pf (the pci clock is allowed to be 12 pf).
6290 sequence drive, san diego, california 92121-4358 800-755-2622 14 S5933 32-bit pci ?matchmaker? stop# perr# clk rst # c/be0# irdy# devsel# flt# idsel# ad0 par mode frame# trdy# serr# ptburst# ptatn# inta# ptadr# ptwr ptrdy# v ss v ss v ss erd#/scl ewr#/sda ptbe2# ptbe0# ptnum1 ptnum0 be3#/adr1 be2# be1# bpclk be0# sysrst# adr6 adr5 adr4 pci local bus add-on local bus eo4 eo3 eo2 eo1 eo0 nvram bus ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 c/be1# c/be2# c/be3# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 irq# adr2 adr3 select# wr# rd# ptbe1# ptbe3# eo5 56 55 54 52 48 47 46 44 42 40 39 38 36 35 34 32 14 12 8 7 6 4 3 2 158 156 155 154 152 148 147 146 159 144 143 16 24 43 28 20 18 19 160 22 23 139 58 26 142 138 135 10 15 102 9 106 104 57 137 141 69 73 81 89 61 97 101 123 122 116 118 119 120 114 112 107 108 115 103 67 66 64 132 87 63 62 60 75 74 72 1 117 105 93 85 77 65 53 45 37 25 13 5 140 124 126 68 95 94 92 88 86 84 83 82 80 79 78 76 157 145 133 125 100 99 98 96 S5933 matchmaker lock# 27 snv 59 v ss 30 eo6 109 121 129 113 byte-wide nvram data fifo data controls add-on local bus controls device controls v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v dd v dd n/c n/c 50 70 90 110 130 150 11 31 51 71 91 111 131 151 134 136 power & ground req# gnt# wrfull wrfifo# rdempty rdfifo# eo11 eo10 eo9 eo8 eo7 eo12 eo13 fwe/eo14 frf/eo15 fwc#/eq4 eq3 eq2 eq1 eq0 frc#/eq5 amren/eq6 amwen/eq7 149 153 21 17 33 29 49 41 128 127 add-on local bus register controls pass-thru data controls
6290 sequence drive, san diego, california 92121-4358 800-755-2622 15 S5933 32-bit pci ?matchmaker? 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 S5933 160 pqfp dq12 dq13 dq14 dq24 dq15 select# wr# ea3 rd# vdd vss ea2 adr2 adr3 adr4 dq25 adr5 be1# be2# ea1 be3# mode inta# ea0 ad0 ad1 ad2 dq26 ad3 vdd vss eq7/amwen ad4 ad5 ad6 dq27 ad7 c/beo# ad8 eq6/amren p t b e 3 # p t b e 2 # p t b e 1 # d q 2 0 p t b e 0 # p t r d y # p t a t n # e a 9 p t b u r s t # v d d v s s e a 8 p t w r p t a d r # r d e m p t y d q 2 1 r d f i f o # w r f u l l w r f i f o # e a 7 d q 0 d q 1 d q 2 e a 6 d q 3 d q 4 d q 5 d q 2 2 d q 6 v d d v s s e a 5 d q 7 b e 0 # d q 8 d q 2 3 d q 9 d q 1 0 d q 1 1 e a 4 ea10 ptnum1 ptnum0 irq# dq19 sysrst# ewr#/sda erd#/scl ea11 vss vdd adr6 dq18 nc snv nc ea12 flt# rst# bpclk ea13 clk gnt# req# dq17 ad31 ad30 ad29 ea14/fwe vss vdd ad28 ea15/frf ad27 ad26 ad25 dq16 ad24 c/be3# idsel e q 0 a d 2 3 a d 2 2 a d 2 1 d q 3 1 a d 2 0 a d 1 9 a d 1 8 e q 1 v s s v d d a d 1 7 d q 3 0 a d 1 6 c / b e 2 # f r a m e # e q 2 i r d y # t r d y # d e v s e l # e q 3 s t o p # l o c k # p e r r # d q 2 9 s e r r # p a r c / b e 1 # e q 4 / f w c # v s s v d d a d 1 5 e q 5 / f r c # a d 1 4 a d 1 3 a d 1 2 d q 2 8 a d 1 1 a d 1 0 a d 9 p a c k a g e i n f o r m a t i o n 160 pqfp
6290 sequence drive, san diego, california 92121-4358 800-755-2622 16 S5933 32-bit pci ?matchmaker? detail a j radius l h k g b a a c a2 a1 a see detail a 0.10 c -c- seating plane d d1 e e1 pin 1 indicator b e S5933 160 pqfp symbol min nom a a1 a2 d d1 e e1 0.80 l e b c - 0.25 3.17 31.90 bsc 0.65 0.22 0.11 max 4.07 1.03 0.38 0.23 a b g g h j k 3.9 2h 5 0 0 0.13 0.13 0.40 16 7 0.30 28.00 bsc 31.90 bsc 28.00 bsc 0.65 bsc 1.95 bsc - - - - - - - - - - - - - - - - - - p a c k a g e i n f o r m a t i o n 160 pqfp
6290 sequence drive, san diego, california 92121-4358 800-755-2622 17 S5933 32-bit pci ?matchmaker? the material in this document supersedes all previous documentation issued for any of the products included herein. amcc reserves the right to make changes to its products or to discon- tinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to ver- ify, before placing orders, that the information being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patents rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or sys- tems or other critical applications. copyright ? 1998 applied micro circuits corporation
6290 sequence drive, san diego, california 92121-4358 800-755-2622 18 sales and representative offices a p p l i e d m i c r o c i r c u i t s c o r p o r a t i o n s a l e s a n d r e p r e s e n t a t i v e s o f f i c e s united states regional sales managers southwest mike vogel (949) 366-4105 northwest sam laymoun (408) 289-1190 mid-us george amundson (972) 423-7989 northeast dave crary (781) 270-0674 southeast joey carabetta (919) 558-2003 factory application engineers northwest issa shokeh (408) 289-1194 mid-us wes stalcup (972) 422-7174 northeast mike sluyski (781) 270-0674 southeast john king (972) 509-0782 representatives centaur north san jose (408) 894-0182 century tech. sales loveland, oh (513) 677-5088 westlake, oh (216) 808-9171 columbus, oh (614) 433-7500 wexford, pa (412) 934-2326 indianapolis, pa (317) 876-0101 lexington, ky (606) 276-3164 novi, mi (248) 344-2550 cetan timonium, md (410) 453-0969 comprep associates westwood, ma (781) 329-3454 customer 1st bloomington, mn (612) 851-7909 overland, ks (913) 895-9593 delta tech sales hatboro, pa (215) 957-0600 dynamic tech old saybrook, ct (860) 388-0130 era, inc. cammack, ny (516) 543-0510 first source sandy, ut (801) 561-1999 glenn white associates huntsville, al (205) 882-6751 duluth, ga (770) 418-1500 raleigh, nc (919) 848-1931 huntersville, nc (704) 875-3777 harper & two san diego, ca (619) 549-5366 signal hill, ca (562) 424-3030 l-squared ltd. beaverton, or (503) 646-7747 kirkland, wa (206) 525-8555 logic 1 sales, inc. richardson, tx (972) 234-0765 austin, tx (512) 345-2952 houston, tx (281) 444-7594 luscombe eng. co. longmont, co (303) 772-3342 parker, co (303) 814-9725 mega technologies, inc. melbourne, fl (407) 752-6767 tampa, fl (813) 797-8222 wilton manors, fl (954) 563-1882 phase ii marketing, inc. rolling meadows, il (847) 577-9401 brookfield, wi (414) 797-9986 quality components manlius, ny (315) 682-8885 quatra associates phoenix, az (602) 753-5544 albuquerque, nm (505) 296-6781 insight electronics u.s. distributor (800) 677-7716 europe/israel general manager richard matysiak 49-89-92404-217 factory application engineer giovanni castellano 39-2-4986244 representatives denmark dan-contact 45-39-683633 france a2m 33-1-46237900 sildesign 33-1-644-63576 germany tekelec airtronic munich 49-89-51640 hamburg 49-453-429-1150 israel eldis technologies ltd. 972-9-9562666 italy acsis s.r.l. 39-248022522 esco italiana spa 39-2-2409241 netherlands tekelec airtronic b.v. 31-79-346-1430 norway bit elektronikk a.s. 47-66-77-65-00 u.k. amega electronics 44-1256-305-330 sweden dipcom 46-8-752-2480 switzerland ixlogic ag 41-1-434 78 10 pacific asia general manager sunny chow (619) 535-6526 factory application engineer michael sedayao (619) 535-6873 representatives korea buksung ind. co. ltd. 82-2-866-1360 singapore gates engineering pte ltd. 65-299-9937 taiwan hsien johnson trading co. 866-2-2999-8281 promate elec co. ltd. 886-2-6590303 japan teksel co., ltd. 81-35467-9104 hong kong twin-star trading co. 852-2341-4282 canada regional sales manager dave crary (781) 270-0674 factory application engineer mike sluyski (781) 270-0674 representatives electronic sales prof. nepean, ont. (613) 828-6881 toronto, ont. (905) 856-8448 st. laurent, que. (514) 344-0420 australia insight electronics pty ltd. 61-3-9761-3455 new zealand 64-9-636-5984 india interex 91-80-640-663

▲Up To Search▲

Price & Availability of S5933

	To Download S5933 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .